Intel processor roadmap

Lunar Lake MX shall be Intel’s first high-performance CPU to make use of outsourced course of node for x86 cores — reportedly makes use of TSMC’s N3B tech

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Intel’s x86 chips at the moment are forging into new territory — leaked slides printed by outstanding {hardware} leaker @YuuKi_AnS (but shortly eliminated) point out that the compute tile of the Lunar Lake MX processors shall be made utilizing TSMC’s N3B fabrication know-how, marking the primary time Intel has used outsourced course of node tech for its highest-end x86 cores. Intel’s Lunar Lake processors are set to function an all-new microarchitecture designed from the bottom as much as provide breakthrough performance-per-watt effectivity, primarily for cell gadgets, however it’s unclear how previous the slides are — these may replicate an older plan for the sequence.

Based on the slides, Intel’s Lunar Lake MX platform lineup will provide processors with as much as eight general-purpose cores (4 high-performance Lion Cove and 4 Skymont energy-efficient cores), 12MB cache, as much as eight Xe2 GPU clusters, and as much as a six-tile NPU 4.0 AI accelerator. Relying on the ability goal, the platform will help 8W fanless in addition to 17W – 30W fanned designs.

The compute tile will purportedly be produced on TSMC’s 3nm-class N3B course of know-how. In the meantime, Intel itself indicated that its Lunar Lake CPUs will use its personal 18A (1.8nm-class) fabrication course of

(Picture credit score: @YuuKi_AnS/Twitter)

Intel’s Lunar Lake MX platform will retain Intel’s multi-chiplet Foveros3D-interconnected design method. Nonetheless, to cut back its bodily footprint, Intel plans to pack the CPU, GPU, and reminiscence controller into the identical tile whereas placing all the pieces else into the SoC tile, in accordance with the slides.

As well as, Intel’s Lunar Lake MX is aimed primarily at laptops, and it’s set to return with 16GB or 32GB of LPDDR5X-8533 memory-on-package, which is able to additional cut back the platform’s footprint and enhance efficiency.  

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