Intel Shows Granite Rapids CPUs as Specs Leak: 5 Chiplets

Posted on

Intel this week showcased its sixth Era Xeon Scalable ‘Sapphire Rapids’ processors as a part of its superior packaging prowess demonstration. The multi-tile datacenter CPU are attributable to arrive within the first half of 2024 and the corporate is sampling them with its clients. In the meantime, {hardware} leaker @Yuuki_AnS this week revealed specs of ES1 samples of those processors. 

Intel’s sixth Era Xeon Scalable ‘Granite Rapids’ processor employs a disaggregated design with 5 chiplets: three tiles carrying Efficiency cores with 2MB of L2 cache, 4MB of L3 cache, and 4 DDR5 interfaces in addition to two high-speed enter/output (HSIO) tiles. These probably the most subtle Granite Rapids CPUs are projected to characteristic 12 DDR5 reminiscence channels supporting DDR5-6400 and MCR DIMMs, 136 PCIe Gen5 lanes with CXL 2.0 assist, and as much as six UPI hyperlinks. 

(Picture credit score: @Yuuki_AnS/Twitter)

Intel has not formally disclosed the core rely on the Granite Rapids CPUs, however in line with the leak ES1 samples with an eight-channel reminiscence subsystem (i.e., they carry two chiplets) prime at 56 cores with 288MB of cache, which suggests that every tile carries both 28 or 30 cores and two cores per chiplet are disabled for redundance. That mentioned, it’s believable to count on manufacturing Granite Rapids CPUs to characteristic 84 – 90 cores. These cores function at 1.10 GHz – 2.70 GHz relying on the precise mannequin, which is low, however we’re speaking about engineering samples of the CPUs.

(Picture credit score: Intel)

The compute chiplets are made on Intel 3 (3nm-class) course of know-how, whereas HSIO chiplets are fabbed on a 7nm-class manufacturing node, which is a confirmed know-how and is taken into account to be optimum for contemporary I/O chiplets when it comes to efficiency and prices. 

Supply hyperlink

Leave a Reply

Your email address will not be published. Required fields are marked *