San Jose-based NEO Semiconductor has launched 3D X-DRAM. This patented DRAM know-how has the formidable intention to “remedy DRAM’s capability bottleneck and change the complete 2D DRAM market.” In line with firm roadmaps, making use of 3D NAND-like DRAM cell arrays in DRAM will ship 1Tb reminiscence ICs by 2030.
1Tb ICs would imply the potential to slap 2TB onto a single DIMM with relative ease — double-sided DIMMs with eight chips per facet would get there. 4TB utilizing 32 ICs would even be doable. Clearly that is extra for servers than something customers are prone to want inside the subsequent ten years, with many nonetheless getting by with 8GB or 16GB. Be aware that present reminiscence options high out at 128GB per DIMM for registered DDR4 server options, utilizing 32 32Gb ICs. Available DDR5 registered DIMMs presently supply as much as 64GB (32 16Gb ICs), although greater capability modules are on the horizon.
Once more, that is for DRAM, not some sort of Flash NAND. However NEO Semiconductor has developed 3D X-DRAM know-how with no less than some inspiration from 3D NAND. It makes use of what’s claimed to be “the world’s first 3D NAND-like DRAM cell array” for its capability boosting USP. There are key variations although, and NEO has already utilized for the varied patents to guard its IP.
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NEO Semiconductor offers a glimpse at how its new 3D X-DRAM works in its press launch. The brand new reminiscence ICs will use a 3D NAND-like DRAM cell array, however we additionally know that the construction is predicated upon capacitor-less floating physique cell know-how. The agency asserts that this modification “simplifies the method steps and offers a high-speed, high-density, low-cost, and high-yield resolution.”
One vital facet contributing to the probabilities of success are that 3D X-DRAM may be manufactured utilizing modern semiconductor fabrication know-how. Furthermore, the corporate estimates that “3D X-DRAM know-how can obtain 128Gb density with 230 layers, which is eight instances at present’s DRAM density.”
For some perspective on the NEO Semiconductor density claims, Samsung’s present highest density DDR5 DRAM ICs are 16Gb in capability. The South Korean tech agency, an vital participant in each NAND and DRAM, is anticipated to launch 32Gb ICs imminently. Mixed with chip stacking, that ought to allow 1TB reminiscence modules in late 2023 / early 2024. That is quite a bit sooner than NEO’s 2030 launch timeframe, and chip stacking for DRAM may go even greater.