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TMSC’s 3nm Replace: N3P and N3X on Monitor with Density and Efficiency Features

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TSMC disclosed main roadmap updates for its N3 (3-nanometer class) household of course of applied sciences at its 2023 North American Expertise Symposium this week. As TSMC’s remaining high-performance node based mostly on FinFET transistors, N3 will final for a few years and can embody a number of variations, together with N3P, a performance-enhancing optical shrink of N3E, and performance-focused N3X for HPC purposes that tolerate excessive leakage and energy.

TSMC’s mass manufacturing on its N3 (also referred to as N3B) course of expertise is already underway, however this node makes use of excessive ultraviolet lithography on as much as 25 layers and may even use EUV double patterning, which makes it a selected costly node to make use of. In consequence, TSMC expects the vast majority of its shoppers to make use of N3E, which may use EUV on as much as 19 layers, doesn’t use double patterning EUV, has a wider course of window, and higher yields. N3E, which will likely be used for top quantity manufacturing in H2 2023, will even be the bottom for TSMC’s additional 3nm evolution. 

(Picture credit score: TSMC)

Step one in that evolution will likely be N3P. This expertise will largely be an optical shrink of N3E that can function another refinements enabling a 5% efficiency enhance on the similar leakage, a 5% to 10% energy discount on the similar clocks, and a 4% increased transistor density for a ‘combined’ chip consisting of fifty% logic, 30% SRAM, and 20% analog circuits.

As an optical shrink of N3E, N3P preserves its design guidelines, permitting chip designers to reuse N3E IP on the brand new node. That is reasonably necessary as IP design corporations like Ansys, Cadence, and Synopsys have already got numerous IP aimed toward N3E chips. In the meantime, optical shrink implies on density enhancements for every kind of transistors and circuits, together with SRAM, a kind of circuits that has struggled to shrink within the latest years (one thing notably unhealthy for contemporary SRAM-intensive designs). N3P will likely be prepared for mass manufacturing in 2024.


(Picture credit score: TSMC)

Following N3P, TSMC plans to additional develop its N3 household and department it into high-performance computing purposes like CPUs and GPUs with N3X. This fabrication course of is projected to offer not less than 5% increased frequencies in comparison with N3P and in addition enable significantly increased voltages, which can additional enhance clocks at the price of increased general leakage.

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Row 0 – Cell 0 N3X vs N3P N3P vs N3E N3E vs N5 N3 vs N5
Velocity Enchancment @ Identical Energy +5% Fmax @ 1.2V +5% +18% +10% ~ 15%
Energy Discount @ Identical Velocity ? -5% ~ -10% -32% -25% ~ -30%
Logic Density similar 1.04x 1.7x 1.6x
HVM Begin 2025 H2 2024 Q2/Q3 2023 H2 2022

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