Though TSMC’s N3 (3nm-class) household of fabrication processes brings an a variety of benefits by way of efficiency and energy, the very excessive prices of the foundry’s preliminary N3 node hampers widespread adoption. Unsurprisingly, the corporate is rumored to be making ready to decrease its quotes for 3nm manufacturing to stimulate curiosity from chip designers, in accordance with a report from MyDrivers.
Whereas at this level any printed TSMC’s N3 quotes and costs must be thought-about rumors, it is doubtless that TSMC’s manufacturing prices on its N3E course of might be decrease than these on its preliminary N3. It stays to be seen how a lot the corporate will cost for manufacturing on different N3-class nodes, equivalent to N3P, N3S, and N3X. Decreasing costs of 3nm manufacturing will appeal to extra prospects to those nodes, however this isn’t one thing that’s going to occur in a single day.
TSMC’s preliminary N3 manufacturing expertise (often known as N3B) is rumored for use solely by Apple as a result of the corporate is the foundry’s largest consumer prepared to undertake modern nodes forward of others. However N3 is an costly expertise to make use of. N3 extensively makes use of excessive ultraviolet (EUV) lithography for as much as 25 layers, in accordance with China Renaissance, and every EUV scanner now prices $150 million – $200 million, relying on configuration. To depreciate fabs geared up with such manufacturing instruments, TSMC has to cost extra for manufacturing on its N3 course of and successors.
Some say that TSMC is likely to be charging as a lot as $20,000 per N3 wafer — up from $16,000 per N5 wafer — and whereas such quotes rely on quite a few elements, the important thing takeaway is that chip manufacturing retains getting costlier. Elevated prices imply decrease income for corporations equivalent to AMD, Broadcom, MediaTek, Nvidia, and Qualcomm, which is why chip builders are reconsidering how they create superior designs and use modern nodes.
“We imagine the significant [N3] ramp-up might be in 2H 2023 when the optimized model, N3E, might be prepared,” wrote Szeho Ng, an analyst with China Renaissance. “Its main prospects in HPC (i.e., AMD, Intel), smartphone (i.e., QCOM, MTK) and ASIC (i.e., MRVL, AVGO, GUC) will doubtless keep in N4/5 and select N3E as their maiden N3 class foray, in our view. In the meantime, we imagine the baseline N3 (aka N3B) adoption might be largely restricted to Apple merchandise.”
To stimulate its companions into utilizing its N3-class course of applied sciences, TSMC is reportedly contemplating decreasing its quotes for these nodes. Particularly, TSMC’s N3E course of makes use of EUV just for as much as 19 layers and options considerably decrease complexity by way of manufacturing, and is thus cheaper to make use of. TSMC may decrease quotes of N3E manufacturing with out harming profitability. N3E offers zero benefits over N5 relating to SRAM cell scaling, which suggests bigger die sizes when in comparison with these made on N3/N3B.
AMD publicly introduced that it deliberate to make use of an N3 node for a few of its Zen 5-based designs due in 2024, and Nvidia is anticipated to undertake N3 for its next-generation Blackwell architecture-based GPUs set to reach across the similar timeframe. As a result of excessive prices, adoption of N3-class nodes is anticipated to be restricted to sure merchandise — so decreasing quotes will most likely make chip designers rethink their adoption technique.
There’s additionally one other challenge with TSMC’s N3: low yields. Some estimate yields are between 60% and 80%, and sources at DigiTimes (by way of Dan Nystedt) point out that they are under 50%. That mentioned, since solely Apple reportedly makes use of this manufacturing expertise and the corporate is understood for being very secretive, any particulars about yields of preliminary N3 chips must be taken with a big grain of salt.