TSMC on Thursday held a “Quantity Manufacturing and Capability Growth Ceremony” at its Fab 18 in within the Southern Taiwan Science Park (STSP). Fab 18 is the place manufacturing of chips utilizing its N3 (3nm-class) course of know-how happen. The foundry says that yields of the 3nm chips it mass produces are good and that the household of its N3 applied sciences will serve its shoppers for a few years to come back.
N3 in HVM
TSMC reportedly initiated excessive quantity manufacturing (HVM) on its N3 fabrication course of in early September. By now the primary batch of chips has been produced and examined, so the formal announcement about quantity manufacturing is mostly designed to point out that the foundry’s 3nm-class course of is sweet for mass manufacturing and chips made on it yield ‘good.’ For TSMC, N3 is a vital household of course of applied sciences as it is going to be the foundry’s final general-purpose node primarily based on FinFET transistors and a node that can serve its prospects for no less than 10 years. Actually, TSMC says that N3 and its successors might be used to construct ‘merchandise with a market worth of $1.5 trillion inside 5 years’ of HVM.
In comparison with TSMC’s N5 manufacturing know-how, the corporate’s N3 manufacturing node guarantees to ship a ten% to fifteen% efficiency enchancment (on the identical energy and transistor depend), cut back energy consumption by 25% – 30% (on the identical frequency and complexity), and improve logic density by round 1.6 instances. In the meantime, N3 barely gives any SRAM scaling because it options an SRAM bitcell measurement of 0.0199 µm^², which is just ~5% smaller in comparison with N5’s 0.021 µm^² SRAM bitcell.
| Header Cell – Column 0 | N3E vs N5 | N3 vs N5 |
|---|---|---|
| Velocity Enchancment @ Identical Energy | +18% | +10% ~ 15% |
| Energy Discount @ Identical Velocity | -34% | -25% ~ -30% |
| Logic Density | 1.7x | 1.6x |
| HVM Begin | Q2/Q3 2023 | H2 2022 |
In the meantime, the primary iteration of TSMC’s 3nm-class fabrication processes — N3 also called N3B — is anticipated for use by early adopters for choose purposes solely because it reportedly has a fairly slender course of window. This might translate into decrease yields for sure designs. Actually, media studies say that almost all of TSMC’s shoppers are actually lining up for N3E manufacturing know-how that improves course of window, will increase efficiency, and additional reduces energy consumption, at the price of SRAM scaling (i.e., decrease transistor density). Apparently, N3E characteristic a a 0.021 µm^² SRAM bitcell, with little or no modifications from N5. This may imply greater die sizes for SRAM intensive designs (the overwhelming majority of CPUs, GPUs, and SoCs).
In the meantime, N3 gives chip designers FinFlex, a robust option to optimize die sizes and efficiency/energy consumption of their chips. FinFlex lets builders to combine and match completely different varieties of normal cells inside one block to precisely optimize efficiency, energy consumption, and space, which might be significantly appreciated by designers of advanced system-on-chips that are inclined to benefit from each transistor efficiency and transistor density.
Finally, TSMC plans so as to add extra nodes to the N3 household. The most recent variations of the method embrace N3P, which guarantees enhanced efficiency, N3S designed to extend transistor density, and N3X with enhanced voltages in addition to additional efficiency optimizations for purposes like CPUs.
Prospects Are Lining Up for N3 Regardless of Excessive Prices
A rumor has it that just about all of TSMC’s most essential prospects, together with AMD, Apple, Broadcom, Intel, MediaTek, Nvidia and Qualcomm are all excited by utilizing TSMC’s N3 nodes, although it’s arduous to inform when every of those chip designers bounce on the foundry’s 3nm bandwagon and with which merchandise. Apple is anticipated to be one of many first shoppers to undertake TSMC’s N3 for certainly one of its premium SoCs, although we don’t know which SoC it’s. In the meantime, AMD intends to undertake N3 for a few of its Zen 5-based merchandise due in 2024, whereas Nvidia will possible use N3 for its next-generation Blackwell architecture-based GPUs due across the identical timeframe.
However utilization of TSMC’s N3 will not be going to be low-cost. Some studies say that the contract maker of chips may cost as a lot as $20,000 per wafer processed utilizing its 3nm-class know-how. TSMC’s pricing in fact will depend on many components, corresponding to volumes, designs, and specs, so take the quantity with a grain of salt.
In the meantime, excessive quotes imply that fabless chip designers could choose to order TSMC’s modern nodes for premium merchandise whereas making extra mainstream units utilizing a confirmed fabrication know-how. For instance, Apple makes use of TSMC’s N4 (4nm-class) manufacturing course of just for its A16 Bionic that powers its flagship iPhone 16 Professional. Against this, the corporate’s iPhone 14 non-Professional continues to depend on the A15 SoC from 2021 that’s made on TSMC’s N5P know-how.
Fab 18 Part 8
Along with asserting that its N3 course of know-how had entered HVM, TSMC additionally held topping ceremony of its Fab 18 section 8 constructing. The corporate makes use of its Fab 18 to make its most superior chips on its N5 and N3 manufacturing nodes. As soon as Fab 18 section 8 is provided with manufacturing instruments, it should considerably increase TSMC’s capability for. Its modern fabrication processes.