With regards to brand-new fabrication nodes, we count on them to extend efficiency, lower down energy consumption, and improve transistor density. However whereas logic circuits have been scaling nicely with the current course of applied sciences, SRAM cells have been lagging behind and apparently nearly stopped scaling at TSMC’s 3nm-class manufacturing nodes. It is a main drawback for future CPUs, GPUs, and SoCs that can probably get costlier due to gradual SRAM cells space scaling.
SRAM Scaling Slows
When TSMC formally launched its N3 fabrication applied sciences earlier this yr, it stated that the brand new nodes would offer 1.6x and 1.7x enhancements in logic density when in comparison with its N5 (5nm-class) course of. What it didn’t reveal is that SRAM cells of the brand new applied sciences nearly don’t scale in comparison with N5, in line with WikiChip, which obtained info from a TSMC paper printed on the Worldwide Electron Gadgets Assembly (IEDM)
TSMC’s N3 options an SRAM bitcell dimension of 0.0199µm^², which is just ~5% smaller in comparison with N5’s 0.021 µm^²SRAM bitcell. It will get worse with the revamped N3E because it comes with a 0.021 µm^² SRAM bitcell (which roughly interprets to 31.8 Mib/mm^²), which suggests no scaling in comparison with N5 in any respect.
In the meantime, Intel’s Intel 4 (initially known as 7nm EUV) reduces SRAM bitcell dimension to 0.024µm^² from 0.0312µm^² in case of Intel 7 (previously referred to as 10nm Enhanced SuperFin), we’re nonetheless speaking about one thing like 27.8 Mib/mm^², which is a bit behind TSMC’s HD SRAM density.
Moreover, WikiChip recollects an Imec presentation that confirmed SRAM densities of round 60 Mib/mm^² on a ‘past 2nm node’ with forksheet transistors. Such course of know-how is years away and between from time to time chip designers must develop processors with SRAM densities marketed by Intel and TSMC (although, Intel 4 will unlikely be utilized by anybody besides Intel anyway).
A great deal of SRAM in Trendy Chips
Trendy CPUs, GPUs, and SoCs use a great deal of SRAM for varied caches as they course of a great deal of knowledge and this can be very inefficient to fetch knowledge from reminiscence, particularly for varied synthetic intelligence (AI) and machine studying (ML) workloads. However even general-purpose processors, graphics chips, and software processors for smartphones carry big caches lately: AMD’s Ryzen 9 7950X carries 81MB of cache in complete, whereas Nvidia’s AD102 makes use of no less than 123MB of SRAM for varied caches that Nvidia publicly disclosed.
Going ahead, the necessity for caches and SRAM will solely improve, however with N3 (which is ready for use for a couple of merchandise solely) and N3E there will probably be no method to scale back die space occupied by SRAM and mitigate larger prices of the brand new node in comparison with N5. Basically, it signifies that die sizes of high-performance processors will improve, and so will their prices. In the meantime, similar to logic cells, SRAM cells are liable to defects. To some extent chip designers will have the ability to alleviate bigger SRAM cells with N3’s FinFlex improvements (mixing and matching totally different sorts of FinFETs in a block to optimize it for efficiency, energy, or space), however at this level we will solely guess what sort of fruits it will convey.
TSMC plans to convey its density-optimized N3S course of know-how that guarantees to shrink SRAM bitcell dimension in comparison with N5, however that is set to occur in circa 2024 and we ponder whether this one will present sufficient logic efficiency for chips designed by AMD, Apple, Nvidia and Qualcomm.
One of many methods to mitigate slowing SRAM space scaling by way of prices goes multi-chiplet design and disaggregate bigger caches into separate dies made on a less expensive node. That is one thing that AMD does with its 3D V-Cache, albeit for a barely totally different motive (for now). One other means is to make use of various reminiscence applied sciences like eDRAM or FeRAM for caches, although the latter have their very own peculiarities.
In any case, it seems to be like slowing of SRAM scaling with FinFET-based nodes at 3nm and past appears to be a significant problem for chip designers within the coming years.