Intel launched 9 analysis papers at IEDM 2022 that lay the groundwork for future chip designs as the corporate appears to be like to ship on its promise of creating processors with over a trillion transistors by 2030.
The analysis consists of new 2D supplies for transistors, new 3D packaging expertise that narrows the efficiency and energy hole between chiplet and single-die processors to a nearly-imperceptible vary, transistors that ‘do not forget’ when energy is eliminated, and embedded recollections that may be stacked straight on high of transistors and retailer multiple bit per cell, amongst different improvements.
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Intel’s Parts Analysis (CR) Group lays the preliminary groundwork for the corporate’s future applied sciences, however not all of those initiatives will end in merchandise that ship to market. Those who do come to market would sometimes arrive in 5 to 10 years.
The group has an unimaginable monitor file of improvements which have already come to market, like FinFET, which revolutionized transistor design for your entire trade, strained silicon, Hello-Okay metallic gate, and lots of others. Intel already has a number of different applied sciences on its roadmap, together with RibbonFET Gate All Round (GAA) transistors, PowerVia back-side energy supply, EMIB, and Foveros Direct, which all hail from this analysis group.
The group submitted 9 analysis papers at this 12 months’s 68th-Annual IEEE Worldwide Electron Gadgets Assembly, and beneath, we’ll cowl a number of of them in barely extra element. Nevertheless, Intel hasn’t but introduced the papers on the convention, so that is broad protection of the matters.
The tempo of transistor density will increase continues roughly consistent with Moore’s Regulation, however the economics of at present’s chips usually are not enhancing on the similar tempo — the value per transistor is rising as we transfer to denser nodes. As well as, poor scaling of some chip components, like analog and caches, complicates issues additional. As such, the trade is shifting en masse to chiplet-based designs for high-performance chips.
The overriding objective of any chiplet-based design is to protect one of the best attributes of the facility consumption and efficiency (latency, bandwidth) of the info pathways within a single-die monolithic processor whereas tapping the financial advantages of utilizing a chiplet-based method, like elevated yield from smaller dies fabbed on a modern course of and the flexibility to make use of older, cheaper nodes for among the different features that see lesser density enhancements.
As such, the battleground for semiconductor supremacy is shifting from the pace of the transistors to the efficiency of the interconnects, with new applied sciences like silicon interposers (EMIB) and hybrid bonding methods coming to the forefront to enhance economics.
Nevertheless, these approaches nonetheless end in inevitable efficiency, energy, and value tradeoffs, which Intel’s new ‘Quasi-Monolithic Chips’ (QMC) 3D packaging tech appears to be like to resolve. Because the identify implies, Intel’s QMC goals to supply practically the identical traits because the interconnects which might be constructed proper right into a single die.
QMC is a brand new hybrid bonding approach that options sub-3 micron pitches and leads to a 10X enhance in energy effectivity and efficiency density over the analysis Intel submitted eventually 12 months’s IEDM. That earlier paper lined an method with 10-micron pitches, which was already a 10X enchancment. As such, Intel has discovered a pathway to a 100X enchancment in only a few years, exhibiting that the corporate’s work in hybrid bonding is accelerating quickly. QMC additionally permits a number of chiplets to be stacked vertically atop each other, as seen within the graphic above.
This paper outlines unimaginable interconnect densities of a whole bunch of 1000’s of connections per sq. millimeter and energy consumption (measured in picojoules per bit – Pj/b) that rivals what we see in monolithic processors. As well as, the brand new paper outlines a number of new supplies and processes that might be used to fabricate such units, paving the best way for real-world units.
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Intel’s course of roadmap already dips beneath the nanometer scale to the Angstrom scale, and although the node naming conventions have way back misplaced their relation to precise bodily measurements of the transistors, it’s clear {that a} radical new method might be wanted for continued scaling. Many of the trade is betting on a shift to 2D atomic channels sooner or later, however as with all new tech, there might be many steps to such a radical change.
As we speak’s chip supplies, like silicon, are comprised of three-dimensional crystals, which implies atoms are bonded in all three dimensions, thus presenting a elementary restrict to shrinking. In distinction, 2D supplies are engaging as a result of all the atoms are bonded in a single airplane, thus enabling options to be constructed with as small as three atoms of thickness.
Enter Intel’s analysis into 2D supplies that it might use for 3D GAA transistors. As a refresher, present GAA designs include stacked horizontal silicon nanosheets, with every nanosheet surrounded solely by a gate. This ‘gate-all-around’ (GAA) approach reduces voltage leakage that forestalls switching off the transistors. That is changing into extra of a problem as transistors shrink — even when the gate surrounds the channel on three sides, as we see with FinFET transistors.
Intel manufacturers its GAA design as RibbonFET, which is at the moment deliberate to reach within the first half of 2024. Nevertheless, shifting past RibbonFET would require additional improvements, and this 2D analysis suits the invoice of a possible pathway.
Intel’s paper describes a Gate All Round (GAA) stacked nanosheet construction with channel supplies (nanosheets/nanoribbons) that measure a mere three atoms thick and may function at room temperature with low leakage present.
The thinness of 2D channel supplies makes establishing {an electrical} connection to a nanoribbon a frightening job, so Intel additionally modeled electrical contact topologies for 2D supplies. It is a key step to understanding the properties of the 2D supplies and the way they perform, thus permitting the corporate to precisely mannequin additional developments.
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Reminiscence in all varieties is an integral a part of computing, nevertheless it additionally consumes loads of the facility price range at each the chip and system degree whereas additionally being a limiting issue for efficiency.
Intel additionally performed the world’s first purposeful demonstration of 3D-stacked ferroelectric reminiscence. Probably the most spectacular facet of this tech is that ferroelectric trench capacitors will be stacked vertically on the logic die atop the transistors. That permits layering the reminiscence atop the logic components as an alternative of being in its personal distinct area, as we see with different forms of embedded reminiscence, like SRAM used for L1 and L2 caches.
Ferroelectric reminiscence additionally permits the same functionality to what we see with NAND flash — the flexibility to retailer a number of bits of information in a construction that might sometimes solely retailer one bit. On this case, Intel demonstrated the flexibility to retailer 4 bits per trench.
Naturally, this method would enhance each bandwidth and reminiscence density whereas lowering latency, yielding a lot bigger and far sooner on-chip caches.
In the identical vein as {the electrical} contacts modeling for 2D buildings, Intel additionally shared its modeling efforts for combined phases and defects for ferroelectric hafnia units, which is able to, in flip, additional the corporate’s personal analysis and growth processes.
Intel can be researching transistors that ‘do not forget,’ which means they do not lose their information (on/off state) after they lose energy. That is akin to any non-volatile storage, like NAND, that may retain its state when energy is eliminated, nevertheless it comes within the type of a logic transistor. Intel says it has hurdled two of the three roadblocks to utilizing this expertise at room temperature. We’re significantly trying ahead to this presentation.
Intel’s different papers on the occasion define different analysis areas, like GaN-on-silicon wafers that may allow future applied sciences past 5G, and higher methods to retailer quantum info to create higher qubits for quantum computing.
It has been 75 years because the transistor altered the course of historical past, and Intel’s Dr. Ann Kelleher, the VP and GM of Know-how Improvement, may also give a particular deal with at IEDM on Monday. The “Celebrating 75 Years of the Transistor! A Have a look at the Evolution of Moore’s Regulation Innovation” presentation takes place at 9:45 am PT on Monday, December 5. We’ll observe up with protection of that presentation quickly.