Alphawave says it has taped out one of many trade’s first chips (opens in new tab) made utilizing TSMC’s N3E fabrication know-how, the second era of a 3nm-class course of node. The chip has been produced by TSMC (Taiwan Semiconductor Manufacturing Co.) and has efficiently handed all the required assessments. It will likely be demonstrated at TSMC’s OIP discussion board later this week.
The chip in query is the Alphawave IP ZeusCORE100 1-112Gbps NRZ/PAM4 Serialiser-Deserialiser (SerDes) that helps quite a few requirements set to be well-liked within the coming years. That features 800G Ethernet, OIF 112G-CEI, PCIe 6.0, and CXL3.0. The SerDes is alleged to assist extra-long channels to allow versatile connectivity options for next-generation servers.
“Alphawave is proud to be among the many first to make the most of TSMC’s most superior 3nm know-how,” stated Tony Pialis, president and CEO of Alphawave. “Our partnership continues to convey modern, high-speed connectivity know-how that may energy probably the most superior knowledge facilities, and we’re excited to showcase these options on the TSMC OIP Discussion board occasion.”
| N3E vs N5 | N3 vs N5 | |
| Velocity Enchancment @ Similar Energy | +18% | +10% ~ 15% |
| Energy Discount @ Similar Velocity | -34% | -25% ~ -30% |
| Logic Density | 1.7x | 1.6x |
| HVM Begin | Q2/Q3 2023 | H2 2022 |
TSMC intends to introduce 5 3nm class course of applied sciences within the subsequent two or three years. The primary era vanilla N3 node is anticipated for use for a number of designs by TSMC’s alpha clients (learn: Apple), whereas the second era N3E will characteristic an improved course of window, which implies quicker time to yield, elevated yields, greater efficiency, and decrease energy.
N3E is anticipated to be adopted significantly extra extensively than vanilla N3, however its mass manufacturing is scheduled to begin in mid-2023 or Q3 2023, a few yr after TSMC initiates excessive quantity manufacturing (HVM) utilizing its N3 manufacturing node.
Like all Serialiser-Deserialiser chips, Alphawave IP’s SerDes is a comparatively small piece of silicon that may make the most of a modern course of know-how. Such designs can be utilized as a “pipe cleaner” to be taught the peculiarities of the manufacturing node. To that finish, it makes excellent sense for Alphawave to make its ZeusCORE100 on TSMC’s N3E course of.
After TSMC begins N3E HVM subsequent yr, it plans to supply three extra 3nm class nodes, together with performance-oriented N3P, N3S fabrication know-how for chips that want excessive transistor density, and N3X manufacturing course of for performance-demanding purposes, corresponding to microprocessors.