Researchers Benchmark Experimental RISC-V Supercomputer

Researchers Benchmark Experimental RISC-V Supercomputer

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A bunch of researchers from the Università di Bologna and Cineca has explored an experimental eight-node 32-core RISC-V supercomputer cluster. The demonstration confirmed that even a bunch of humble SiFive’s Freedom U740 system-on-chips might run supercomputer purposes at comparatively low energy. Furthermore, the cluster labored properly and supported a baseline high-performance computing stack.

Want for RISC-V

One of many benefits of the open-source RISC-V instruction set structure is the relative simplicity of constructing a extremely customized RISC-V core aimed toward a specific utility that may provide a really aggressive stability between efficiency, energy consumption, and price. It makes RISC-V appropriate for rising purposes and varied high-performance computing tasks that cater to a specific workload. The group explored the cluster to show that RISC-V-based platforms can operate for high-performance computing (HPC) from a software program perspective.



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